1. Field of the Invention
The present invention relates to the semiconductor field, and specifically, to a semiconductor device and a manufacturing method therefor.
2. Description of the Related Art
With the continuous development of semiconductor techniques, carrier mobility enhancement techniques have been widely investigated and utilized. Carrier mobility improvement in a channel region may increase the driving current of a MOS device, thus improving device performance.
One effective mechanism for improving carrier mobility is to produce stress in a channel region. To this end, embedded SiGe techniques have been widely applied to improve the performance of PMOS devices. By embedding SiGe material in PMOS source and drain regions, embedded SiGe techniques may apply compressive stress to the channel region, causing significant PMOS performance improvement.
In embedded SiGe techniques, stress applied to the channel region can be increased by increasing the content of Ge in the embedded SiGe material. However, the large difference of Ge content between a Si substrate and the embedded SiGe material (for example, when the content of Ge in the SiGe material embedded in the source/drain regions exceeds 30 at. % (atomic percent)) may cause substantial stacking faults to occur on the interface between Si and SiGe, deteriorating the device's performance.
Therefore, a new technique is needed for eliminating or at least reducing the occurrence of stacking faults while providing high content of Ge in embedded SiGe source/drain regions.